View CY7C1484BV33-250BZXC_8513938.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

cy7c1484bv33 72-mbit (2 m 36) pipelined dcd sync sram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-75351 rev. *b revised january 9, 2013 72-mbit (2 m 36) pipelined dcd sync sram features supports bus operation up to 250 mhz available speed grade is 250 mhz registered inputs and outputs for pipelined operation optimal for performance (double cycle deselect) depth expansion wit hout wait state 3.3 v core power supply (v dd ) 2.5 v and 3.3 v i/o operation fast clock to output times ? 3.0 ns (for 250 mhz device) provide high performance 3-1-1-1 access rate user selectable burst counter supporting intel ? pentium ? interleaved or linear burst sequences separate processor and controller address strobes synchronous self timed writes asynchronous output enable cy7c1484bv33 available in pb-free 165-ball fbga package ieee 1149.1 jtag comp atible boundary scan ?zz? sleep mode option functional description the cy7c1484bv33 sram integrates 2 m 36 sram cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. all synchronous inputs are gated by registers controlled by a positive edge triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, address pipelining chip enable (ce 1 ), depth expansion chip enables (ce 2 and ce 3 ), burst control inputs (adsc , adsp , and adv ), write enables (bw x , and bwe ), and global write (gw ). asynchronous inputs include the output enable (oe ) and the zz pin. addresses and chip enables are registered at rising edge of clock when either address strobe processor (adsp ) or address strobe controller ( adsc ) are active. subsequent burst addresses can be internally generated as controlled by the advance pin (adv ). address, data inputs, and write controls are registered on-chip to initiate a self timed write cycle. this part supports byte write operations (see pin definitions on page 5 and truth table on page 8 for more informat ion). write cycles can be one to four bytes wide as controlled by the byte write control inputs. gw active low causes all bytes to be written. this device incorporates an additional pipelined enable register, which delays turning off the output buff ers an additional cycle when a deselect is executed. this f eature allows depth expansion without penalizing system performance. the cy7c1484bv33 operates from a +3.3 v core power supply while all outputs operate with a +3.3 v or a +2.5 v supply. all inputs and outputs are jedec standard jesd8-5 compatible. selection guide description 250 mhz unit maximum access time 3.0 ns maximum operating current 500 ma maximum cmos standby current 120 ma
cy7c1484bv33 document number: 001-75351 rev. *b page 2 of 30 logic block diagram ? cy7c1484bv33 address register adv clk burst counter and logic clr q1 q0 adsp adsc mode bw d bw c bw b bw a bwe gw ce 1 ce 2 ce 3 oe dq d, dqp d byte write register dq c ,dqp c byte write register dq b ,dqp b byte write register dq a, dqp a byte write register enable register pipelined enable output registers sense amps memory array output buffers dq a, dqp a byte write driver dq b ,dqp b byte write driver dq c ,dqp c byte write driver dq d, dqp d byte write driver input registers a 0,a1,a a[1:0] sleep control zz e 2 dqs dqp a dqp b dqp c dqp d
cy7c1484bv33 document number: 001-75351 rev. *b page 3 of 30 contents pin configurations ........................................................... 4 pin definitions .................................................................. 5 functional overview ........................................................ 6 single read accesses ................................................ 6 single write accesses initia ted by adsp ................... 6 single write accesses initiate d by adsc ................... 6 burst sequences ......................................................... 7 sleep mode ................................................................. 7 interleaved burst address table (mode = floating or v dd ) .................................................. 7 linear burst address table (mode = gnd) ............... 7 zz mode electrical characteri stics .............................. 7 truth table ........................................................................ 8 truth table for read/write .............................................. 9 ieee 1149.1 serial boundary sc an (jtag) ... ........... .... 10 disabling the jtag feature ...................................... 10 test access port (tap) ............................................. 10 performing a tap r eset .......... .............. .......... 10 tap registers ...................................................... 10 tap instruction set ................................................... 10 tap controller state diagram ....................................... 12 tap controller block diagram ...................................... 13 tap timing ...................................................................... 13 tap ac switching characteristics ............................... 14 3.3 v tap ac test conditions ....................................... 15 3.3 v tap ac output load equivalent ......................... 15 2.5 v tap ac test conditions ....................................... 15 2.5 v tap ac output load equivalent ......................... 15 tap dc electrical characteristics and operating conditions ..................................................... 15 identification register definitions ................................ 16 scan register sizes ....................................................... 16 identification codes ....................................................... 16 boundary scan exit order ...... ....................................... 17 maximum ratings ........................................................... 18 operating range ............................................................. 18 electrical characteristics ............................................... 18 capacitance .................................................................... 19 thermal resistance ........................................................ 19 ac test loads and waveforms ..................................... 20 switching characteristics .............................................. 21 switching waveforms .................................................... 22 ordering information ...................................................... 26 ordering code definitions ..... .................................... 26 package diagrams .......................................................... 27 acronyms ........................................................................ 28 document conventions ................................................. 28 units of measure ....................................................... 28 document history page ................................................. 29 sales, solutions, and legal information ...................... 30 worldwide sales and design s upport ......... .............. 30 products .................................................................... 30 psoc solutions ......................................................... 30
cy7c1484bv33 document number: 001-75351 rev. *b page 4 of 30 pin configurations figure 1. 165-ball fbga (15 17 1.4 mm) pinout cy7c1484bv33 (2 m 36) 234 567 1 a b c d e f g h j k l m n p r tdo nc/288m nc/144m dqp c dq c dqp d nc dq d ce 1 bw b ce 3 bw c bwe a ce 2 dq c dq d dq d mode nc dq c dq c dq d dq d dq d a a v ddq bw d bw a clk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck v ss tdi a a dq c v ss dq c v ss dq c dq c nc v ss v ss v ss v ss nc v ss a1 dq d dq d nc nc v ddq v ss tms 891011 a adv a adsc nc oe adsp a nc/576m v ss v ddq nc/1g dqp b v ddq v dd dq b dq b dq b nc dq b nc dq a dq a v dd v ddq v dd v ddq dq b v dd nc v dd dq a v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq dq a v ddq a a v ss a a a dq b dq b dq b zz dq a dq a dqp a dq a a v ddq a a0 a v ss a
cy7c1484bv33 document number: 001-75351 rev. *b page 5 of 30 pin definitions pin name i/o description a 0 , a 1 , a input- synchronous address inputs used to select one of the address locations . sampled at the rising edge of the clk if adsp or adsc is active low, and ce 1 , ce 2 , and ce 3 are sampled active. a1:a0 are fed to the 2-bit counter. bw a , bw b bw c , bw d input- synchronous byte write select inputs, active low . qualified with bwe to conduct byte writes to the sram. sampled on the rising edge of clk. gw input- synchronous global write enable input, active low . when asserted low on the rising edge of clk, a global write is conducted (all bytes are written, regardless of the values on bw x and bwe ). bwe input- synchronous byte write enable input, active low . sampled on the rising edge of clk. this signal must be asserted low to conduct a byte write. clk input- clock clock input . capture all synchronous inputs to the device. also used to increment the burst counter when adv is asserted low during a burst operation. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select or deselect the device. adsp is ignored if ce 1 is high. ce 1 is sampled only when a new external address is loaded. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select or dese lect the device. ce 2 is sampled only when a new external address is loaded. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select or deselect the device. ce 3 is sampled only when a new external address is loaded. oe input- asynchronous output enable, asynchronous input, active low . controls the direction of the i/o pins. when low, the i/o pins behave as outputs. when deasserted hi gh, dq pins are tri-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging fr om a deselected state. adv input- synchronous advance input signal, sampled on the rising edge of clk, active low . when asserted, it automatically increments t he address in a burst cycle. adsp input- synchronous address strobe from processor, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a1:a0 are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. asdp is ignored when ce 1 is deasserted high. adsc input- synchronous address strobe from controller, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a1:a0 are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. zz input- asynchronous zz ?sleep? input, active high . when asserted high, places the device in a non time-critical ?sleep? condition with data integrity preserved. for normal operation, this pin must be low or left floating. zz pin has an internal pull down. dqs, dqps i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip da ta register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by the addresses presente d during the previous clo ck rise of the read cycle . the direction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dqs and dqp x are placed in a tri-state condition. v dd power supply power supply inputs to the core of the device . v ss ground ground for the core of the device . v ddq i/o power supply power supply for the i/o circuitry . mode input- static selects burst order . when tied to gnd, selects linear burst sequence. when tied to v dd or left floating, selects interleaved burst sequence. this is a strap pin and must remain static during device operation. mode pin has an internal pull up. tdo jtag serial output synchronous serial data-out to the jtag circuit . delivers data on the negative edge of tck. if the jtag feature is not used, this pin must be disconnected.
cy7c1484bv33 document number: 001-75351 rev. *b page 6 of 30 functional overview all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by the ri sing edge of the clock. the cy7c1484bv33 supports secondary cache in systems using either a linear or interleaved burst sequence. the interleaved burst order supports pentium and i486? processors. the linear burst sequence is suited for processors that use a linear burst sequence. the burst order is user selectable and is determined by sampling the mode input. accesses are initiated with either the processor address strobe (adsp ) or the controller address strobe (adsc ). address advancement through the burst sequence is controlled by the adv input. a 2-bit on-chip wraparound burst co unter captures the first address in a burst sequence and automat ically increments the address for the rest of the burst access. byte write operations are qualif ied with the byte write enable (bwe ) and byte write select (bw x ) inputs. a global write enable (gw ) overrides all byte write inputs and writes data to all four bytes. all writes are simp lified with on-chi p synchronous self timed write circuitry. synchronous chip selects ce 1 , ce 2 , ce 3, and an asynchronous output enable (oe ) provide easy bank selection and output tri-state control. adsp is ignored if ce 1 is high. single read accesses this access is initiated when the following conditions are satisfied at clock rise: (1) adsp or adsc is asserted low, (2) chip selects are all asserted active, and (3) the write signals (gw , bwe ) are all deasserted high. adsp is ignored if ce 1 is high. the address presented to the address inputs is stored into the address advancement logic and the address register while being presented to the memory core. the corresponding data is allowed to propagate to the input of the output registers. at the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within t co if oe is active low. the only exception occurs when the sram is emerging from a deselected state to a selected state; its outputs are always tri-stated during the fi rst cycle of the access. after the first cycle of t he access, the oe signal controls the outputs. consecutive single read cycles are supported. the cy7c1484bv33 is a double cycle deselect part. after the sram is deselected at clock rise by the chip select and either adsp or adsc signals, its output tri-st ates immediately after the next clock rise. single write accesses initiated by adsp this access is initiated when both the following conditions are satisfied at clock rise: (1) adsp is asserted low and (2) chip select is asserted active. the address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. the write signals (gw , bwe , and bw x ) and adv inputs are ignored during this first cycle. adsp triggered write accesses require two clock cycles to complete. if gw is asserted low on th e second clock rise, the data presented to the dq x inputs is written into the corresponding address location in the memory core. if gw is high, then the bwe and bw x signals control the write operation. the cy7c1484bv33 provides byte write capability that is described in the truth table on page 8 . asserting the byte write enable input (bwe ) with the selected byte write input selectively writes to only the desired bytes. bytes not selected during a byte write operation remain unaltered. a synchronous self timed write mechanism is provided to simplify the write operations. because the cy7c1484bv33 is a common i/o device, the output enable (oe ) must be deasserted high before presenting data to the dq inputs. doing so tri-states the output drivers. as a safety precaution, dq are autom atically tri-stated whenever a write cycle is detected, rega rdless of the state of oe . single write accesses initiated by adsc adsc write accesses are initiated when the following conditions are satisfied: (1) adsc is asserted low, (2) adsp is deasserted high, (3) chip select is asserted active, and (4) the appropriate combination of the write inputs (gw , bwe , and bw x ) are asserted active to conduct a write to the desired bytes. adsc triggered write accesse s require a single clock cycle to complete. the address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. the adv input is ignored du ring this cycle. if a global write is conducted, the data presented to the dq x is written into the corresponding address location in the memory core. if a byte write is conducted, only the selected bytes are written. bytes not selected during a byte write operation remain unaltered. a synchronous self timed write mechanism is provided to simplify the write operations. tdi jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not used, this pin can be disconnected or connected to v dd . tms jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not used, this pin can be disconnected or connected to v dd . tck jtag clock clock input to th e jtag circuitry . if the jtag feature is not used, this pin must be connected to v ss . nc ? no connects . not internally connected to the die. 14 4m, 288m, 576m, and 1g are address expansion pins and are not internally connected to the die. pin definitions (continued) pin name i/o description
cy7c1484bv33 document number: 001-75351 rev. *b page 7 of 30 because the cy7c1484bv33 is a common i/o device, the output enable (oe ) must be deasserted high before presenting data to the dq x inputs. doing so tri-states the output drivers. as a safety precaution, dq x are automatically tri-stated whenever a write cycle is detected, regardless of the state of oe . burst sequences the cy7c1484bv33 provides a 2-bit wraparound counter, fed by a [1:0] , that implements either an interleaved or linear burst sequence. the interleaved burst sequence is designed specifically to support intel pentium applications. the linear burst sequence is designed to s upport processors that follow a linear burst sequence. the burs t sequence is user selectable through the mode input. both read and write burst operations are supported. asserting adv low at clock rise auto matically increments the burst counter to the next addre ss in the burst sequence. both read and write burst operations are supported. sleep mode the zz input pin is asynchronous. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data integrity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected before enteri ng the ?sleep? mode. ce s, adsp , and adsc must remain inactive for the duration of t zzrec after the zz input returns low . interleaved burst address table (mode = floating or v dd ) first address a1:a0 second address a1:a0 third address a1:a0 fourth address a1:a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1:a0 second address a1:a0 third address a1:a0 fourth address a1:a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min max unit i ddzz sleep mode standby current zz > v dd ? ? 0.2 v ? 120 ma t zzs device operation to zz zz > v dd ? 0.2 v ? 2t cyc ns t zzrec zz recovery time zz < 0.2 v 2t cyc ?ns t zzi zz active to sleep current t his parameter is sampled ? 2t cyc ns t rzzi zz inactive to exit sleep curr ent this parameter is sampled 0 ? ns
cy7c1484bv33 document number: 001-75351 rev. *b page 8 of 30 truth table the truth table for cy7c1484bv33 follows. [1, 2, 3, 4, 5] operation address used ce 1 ce 2 ce 3 zz adsp adsc adv write oe clk dq deselect cycle, power down none h x x l x l x x x l?h tri-state deselect cycle, power down none l l x l l x x x x l?h tri-state deselect cycle, power down none l x h l l x x x x l?h tri-state deselect cycle, power down none l l x l h l x x x l?h tri-state deselect cycle, power down none l x h l h l x x x l?h tri-state sleep mode, power down none x x x h x x x x x x tri-state read cycle, begin burst external l h l l l x x x l l?h q read cycle, begin burst external l h l l l x x x h l?h tri-state write cycle, begin burst external l h l l h l x l x l?h d read cycle, begin burst external l h l l h l x h l l?h q read cycle, begin burst external l h l l h l x h h l?h tri-state read cycle, continue burst next x x x l h h l h l l?h q read cycle, continue burst next x x x l h h l h h l?h tri-state read cycle, continue burst next h x x l x h l h l l?h q read cycle, continue burst next h x x l x h l h h l?h tri-state write cycle, continue burst next x x x l h h l l x l?h d write cycle, continue burst next h x x l x h l l x l?h d read cycle, suspend burst current x x x l h h h h l l?h q read cycle, suspend burst current x x x l h h h h h l?h tri-state read cycle, suspend burst current h x x l x h h h l l?h q read cycle, suspend burst current h x x l x h h h h l?h tri-state write cycle, suspend burst current x x x l h h h l x l?h d write cycle, suspend burst current h x x l x h h l x l?h d notes 1. x = don?t care, h = logic high, l = logic low. 2. write = l when any one or more byte write enable signals and bwe = l or gw = l. write = h when all byte write enable signals, bwe , gw = h. 3. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 4. the sram always initiates a read cycle when adsp is asserted, regardless of the state of gw , bwe , or bw x . writes can occur only on subsequent clocks after the adsp or with the assertion of adsc . as a result, oe must be driven high prior to the start of the write cycle to enable the outputs to tri-state. oe is a don?t care for the remainder of the write cycle. 5. oe is asynchronous and is not sampled with the clock rise. it is masked inte rnally during write cycles. during a read cycle all d ata bits are tri-state when oe is inactive or when the device is deselected, and all data bits behave as output when oe is active (low).
cy7c1484bv33 document number: 001-75351 rev. *b page 9 of 30 truth table for read/write the read/write truth table for cy7c1484bv33 and follows. [6, 7] function (cy7c1484bv33) gw bwe bw d bw c bw b bw a read h h x x x x read hlhhhh write byte a ? (dq a and dqp a )hlhhhl write byte b ? (dq b and dqp b )hlhhlh write bytes b, a h l h h l l write byte c ? (dq c and dqp c )hlhlhh write bytes c, a h l h l h l write bytes c, b h l h l l h write bytes c, b, a h l h l l l write byte d ? (dq d and dqp d )hllhhh write bytes d, a h l l h h l write bytes d, b h l l h l h write bytes d, b, a h l l h l l write bytes d, c h l l l h h write bytes d, c, a h l l l h l write bytes d, c, b h l l l l h write all bytes h l l l l l write all bytes l x x x x x notes 6. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 7. table includes only a partial listing of the byte write combinations. any combination of bw x is valid. appropriate write is bas ed on which byte write is active.
cy7c1484bv33 document number: 001-75351 rev. *b page 10 of 30 ieee 1149.1 serial boundary scan (jtag) the cy7c1484bv33 incorporates a serial boundary scan test access port (tap). this port op erates in accordance with ieee standard 1149.1-1990 but does not have the set of functions required for full 1149.1 complia nce. these functions from the ieee specification are excluded because their inclusion places an added delay in the critical speed path of the sram. note that the tap controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant taps. the tap operates using jedec standard 3.3 v or 2.5 v i/o logic levels. the cy7c1484bv33 contains a tap controller, instruction register, boundary scan register, bypass register, and id register. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tie tck low (v ss ) to prevent device clocking. tdi and tms are internally pulled up and may be unconnected. they may alternatively be connected to v dd through a pull up resistor. tdo must be left unconnected. during power up, the device comes up in a reset state, which does not interfere with the operation of the device. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tc k. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input gives commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this ball unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi ball serially inputs information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information about loading the instruction re gister, see the tap controller state diagram on page 12 . tdi is internally pulled up and can be unconnected if the tap is unused in an applicatio n. tdi is connected to the most significant bit (msb) of any register. test data-out (tdo) the tdo output ball serially cloc ks data-out from the registers. whether the output is active depends on the current state of the tap state machine (see identification codes on page 16 ). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. performing a tap reset perform a reset by forcing tms high (v dd ) for five rising edges of tck. this reset does no t affect the operation of the sram and may be performed while the sram is operating. during power up, the tap is reset internally to ensure that tdo comes up in a high z state. tap registers registers are connected between the tdi and tdo balls to scan the data in and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. instruction register three-bit instructions are serial ly loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls, as shown in the tap controller block diagram on page 13 . during power up, the instru ction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is pl aced in a reset state, as described in the previous section. when the tap controller is in th e capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to enable fault isolation of the board-level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single bit register that is placed between the tdi and tdo balls. this enables shifting of data through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram . the x36 configuration has a 73-bit long register and the x18 configuration has a 54-bit long register. the boundary scan register is loaded with the contents of the ram i/o ring when the tap controll er is in the capture-dr state and is then placed between the tdi and tdo balls when the controller moves to the shift-dr state. the extest, sample/preload, and sample z instructions are used to capture the contents of the i/o ring. the boundary scan exit order on page 17 show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register . the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id regist er has a vendor code and other information described in identification register definitions on page 16 . tap instruction set overview eight different instructions are po ssible with the 3-bit instruction register. all combinations are listed in identification codes on page 16 . three of these instructio ns are listed as reserved and must not be used. the other five instructions are described in detail in this section.
cy7c1484bv33 document number: 001-75351 rev. *b page 11 of 30 the tap controller used in this sram is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. the tap controller cannot be used to load address data or control signals into the sram and cannot preload the i/o buffers. the sram does not implement the 1149.1 commands extest or intest or the preload portion of sample/preload; rather, it performs a captur e of the i/o ring when these instructions are executed. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo balls. to execute the instruction after it is shifte d in, the tap controller must be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction that is executed whenever the instruction regist er is loaded with all zeros. extest is not implemented in this sram tap controller, and therefore this device is not compliant to 1149.1. the tap controller does recognize an all-zero instruction. when an extest instruction is loaded into the instruction register, the sram respond s as if a sample/preload instruction is loaded. there is one difference between the two instructions. unlike the sam ple/preload instruction, extest places the sram outputs in a high z state. idcode the idcode instruction loads a vendor specific, 32-bit code into the instruction register. it also places the instruction register between the tdi and tdo balls and shifts the idcode out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register at power up or whenever the tap contro ller is in a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo balls when the tap controller is in a shift-dr state. it also places all sram outputs into a high z state. sample/preload sample/preload is a 1149.1 m andatory instruction. the preload portion of this instruction is not implemented, so the device tap controller is not fully 1149.1 compliant. when the sample/preload instruction is loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. be aware that the tap controll er clock only operates at a frequency up to 10 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output may undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this does not harm the device, but there is no guarantee as to the value that may be captured. repeatable results may not be possible. to guarantee that the boundary scan register captures the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller?s capture setup plus hold time (t cs plus t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if th is is an issue, it is still possible to capture all other signals and simply ignore the value of the clk captured in the boundary scan register. after the data is captured, shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo balls. note that because the preload part of the command is not implemented, putting the tap to the update-dr state while performing a sample/preload instruction has the same effect as the pause-dr command. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift- dr state, the bypass register is placed between the tdi and tdo balls. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions.
cy7c1484bv33 document number: 001-75351 rev. *b page 12 of 30 the 0/1 next to each state represents t he value of tms at the rising edge of tck. tap controller state diagram test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0
cy7c1484bv33 document number: 001-75351 rev. *b page 13 of 30 tap controller block diagram bypass register 0 instruction register 0 1 2 identification register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . selection circuitry tck tms tap controller tdi tdo selection circuitry tap tiing figure 2. tap tiing t tl test clock (tck) 123456 t est mode select (tms) t th test data-out (tdo) t cyc test data-in (tdi) t tmsh t tmss t tdih t tdis t tdox t tdov dont care undefined
cy7c1484bv33 document number: 001-75351 rev. *b page 14 of 30 tap ac switchi ng characteristics over the operating range parameter [8, 9] description min max unit clock t tcyc tck clock cycle time 50 ? ns t tf tck clock frequency ? 20 mhz t th tck clock high time 20 ? ns t tl tck clock low time 20 ? ns output times t tdov tck clock low to tdo valid ? 10 ns t tdox tck clock low to tdo invalid 0 ? ns setup times t tmss tms setup to tck clock rise 5 ? ns t tdis tdi setup to tck clock rise 5 ? ns t cs capture setup to tck rise 5 ? ns hold times t tmsh tms hold after tck clock rise 5 ? ns t tdih tdi hold after clock rise 5 ? ns t ch capture hold after clock rise 5 ? ns notes 8. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 9. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns.
cy7c1484bv33 document number: 001-75351 rev. *b page 15 of 30 3.3 v tap ac test conditions input pulse levels ...............................................v ss to 3.3 v input rise and fall times ...................................................1 ns input timing reference levels .. ....................................... 1.5 v output reference levels ................................................ 1.5 v test load termination supply voltage ............................ 1.5 v 2.5 v tap ac test conditions input pulse levels ............ ................................... v ss to 2.5 v input rise and fall time ....................................................1 ns input timing reference levels ... .................................... 1.25 v output reference levels .............................................. 1.25 v test load termination supply vo ltage .......................... 1.25 v 3.3 v tap ac out put load equivalent tdo 1.5v 20pf z = 50 o 50 tdo 1.25v 20pf z = 50 o 50 (0 c < t a < +70 c; v dd = 3.135 v to 3.6 v unless otherwise noted) parameter [11] description test conditions min max unit v oh1 output high voltage i oh = ?4.0 ma, v ddq = 3.3 v 2.4 ? v i oh = ?1.0 ma, v ddq = 2.5 v 2.0 ? v v oh2 output high voltage i oh = ?100 a v ddq = 3.3 v 2.9 ? v v ddq = 2.5 v 2.1 ? v v ol1 output low voltage i ol = 8.0 ma, v ddq = 3.3 v ? 0.4 v i ol = 1.0 ma, v ddq = 2.5 v ? 0.4 v v ol2 output low voltage i ol = 100 a v ddq = 3.3 v ? 0.2 v v ddq = 2.5 v ? 0.2 v v ih input high voltage v ddq = 3.3 v 2.0 v dd + 0.3 v v ddq = 2.5 v 1.7 v dd + 0.3 v v il input low voltage v ddq = 3.3 v ?0.5 0.7 v v ddq = 2.5 v ?0.3 0.7 v i x input load current gnd < v in < v ddq ?5 5 a note 11. all voltages refer to v ss (gnd).
cy7c1484bv33 document number: 001-75351 rev. *b page 16 of 30 identification regi ster definitions bit# 24 is ?1? in the id register definitions for both 2.5 v and 3.3 v versions of the device. instruction field cy7c1484bv33 (2 m 36) description revision number (31:29) 000 describes the version number device depth (28:24) 01011 reserved for internal use architecture/memory type(23:18) 000110 d efines memory type and architecture bus width/density (17:12) 100100 defines width and density cypress jedec id code (11:1) 00000110100 e nables unique identification of sram vendor id register presence indicator (0) 1 indi cates the presence of an id register scan register sizes register name bit size ( 36) instruction 3 bypass 1 id 32 boundary scan order ? 165-ball fbga 73 identification codes instruction code description extest 000 captures i/o ring contents. idcode 001 loads the id register wit h the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures i/o ring contents. places th e boundary scan register between tdi and tdo. forces all sram output drivers to a high z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/preload 100 captures i/o ring contents. places the boundary sca n register between tdi and tdo. does not affect sram operation. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operations.
cy7c1484bv33 document number: 001-75351 rev. *b page 17 of 30 boundary scan exit order (2 m 36) bit # 165-ball id bit # 165-ball id bit # 165-ball id bit # 165-ball id 1c1 21r3 41l10 61b8 2d1 22p2 42k11 62a7 3e1 23r4 43j11 63b7 4d2 24p6 44k10 64b6 5 e2 25 r6 45 j10 65 a6 6f1 26n6 46h11 66b5 7g1 27p11 47g11 67a5 8f2 28r8 48f11 68a4 9g2 29p3 49e11 69b4 10 j1 30 p4 50 d10 70 b3 11 k1 31 p8 51 d11 71 a3 12 l1 32 p9 52 c11 72 a2 13 j2 33 p10 53 g10 73 b2 14 m1 34 r9 54 f10 15 n1 35 r10 55 e10 16 k2 36 r11 56 a10 17 l2 37 n11 57 b10 18 m2 38 m11 58 a9 19 r1 39 l11 59 b9 20 r2 40 m10 60 a8
cy7c1484bv33 document number: 001-75351 rev. *b page 18 of 30 maximum ratings exceeding the maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature .... ............ ............... ?65 ? c to +150 ? c ambient temperature with power applied ... .............. .............. .......... ?55 ? c to +125 ? c supply voltage on v dd relative to gnd .....?0.5 v to +4.6 v supply voltage on v ddq relative to gnd .... ?0.5 v to +v dd dc voltage applied to outputs in tri-state ........................................?0.5 v to v ddq + 0.5 v dc input voltage ................................ ?0.5 v to v dd + 0.5 v current into outputs (low) .... .................................... 20 ma static discharge voltage (mil-std-883, method 3015) .................................. >2001 v latch up current .................................................... >200 ma operating range range ambient temperature v dd v ddq commercial 0 c to +70 c 3.3 v ? ? 5% / + 10% 2.5 v ? 5% to v dd industrial ?40 c to +85 c electrical characteristics over the operating range parameter [12, 13] description test conditions min max unit v dd power supply voltage 3.135 3.6 v v ddq i/o supply voltage for 3.3 v i/o 3.135 v dd v for 2.5 v i/o 2.375 2.625 v v oh output high voltage for 3.3 v i/o, i oh = ?4.0 ma 2.4 ? v for 2.5 v i/o, i oh = ?1.0 ma 2.0 ? v v ol output low voltage for 3.3 v i/o, i ol = 8.0 ma ? 0.4 v for 2.5 v i/o, i ol = 1.0 ma ? 0.4 v v ih input high voltage [12] for 3.3 v i/o 2.0 v dd + 0.3 v v for 2.5 v i/o 1.7 v dd + 0.3 v v v il input low voltage [12] for 3.3 v i/o ?0.3 0.8 v for 2.5 v i/o ?0.3 0.7 v i x input leakage current except zz and mode gnd ? v i ? v ddq ?5 5 ? a input current of mode input = v ss ?30 ? ? a input = v dd ?5 ? a input current of zz input = v ss ?5 ? ? a input = v dd ?30 ? a i oz output leakage current gnd ? v i ? v ddq, output disabled ?5 5 ? a i dd [14] v dd operating supply current v dd = max., i out = 0 ma, f = f max = 1/t cyc 4 ns cycle, 250 mhz ?500ma i sb1 automatic ce power down current ? ttl inputs v dd = max, device deselected, v in ? v ih or v in ? v il f = f max = 1/t cyc 4 ns cycle, 250 mhz ?245ma i sb2 automatic ce power down current ? cmos inputs v dd = max, device deselected, v in ? 0.3v or v in > v ddq ? 0.3v, f = 0 4 ns cycle, 250 mhz ?120ma notes 12. overshoot: v ih(ac) < v dd +1.5 v (pulse width less than t cyc /2). undershoot: v il(ac) > ?2 v (pulse width less than t cyc /2). 13. power up: assumes a linear ramp from 0 v to v dd(minimum) within 200 ms. during this time v ih < v dd and v ddq < v dd . 14. the operation current is calculated with 50% read cycle and 50% write cycle.
cy7c1484bv33 document number: 001-75351 rev. *b page 19 of 30 i sb3 automatic ce power down current ? cmos inputs v dd = max, device deselected, v in ? 0.3 v or v in > v ddq ? 0.3 v, f = f max = 1/t cyc 4 ns cycle, 250 mhz ?245ma i sb4 automatic ce power down current ? ttl inputs v dd = max, device deselected, v in ? v ih or v in ? v il , f = 0 4 ns cycle, 250 mhz ?135ma electrical characteristics (continued) over the operating range parameter [12, 13] description test conditions min max unit capacitance parameter [15] description test conditions 165-ball fbga package unit c address address input capacitance t a = 25 ? c, f = 1 mhz, v dd = 3.3 v, v ddq = 2.5 v 6 pf c data data input capacitance 5pf c ctrl control input capacitance 8pf c clk clock input capacitance 6pf c io input/output capacitance 5pf thermal resistance parameter [15] description test conditions 165-ball fbga package unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. 16.3 ? c/w ? jc thermal resistance (junction to case) 2.1 ? c/w note 15. tested initially and after any design or proc ess change that may affect these parameters.
cy7c1484bv33 document number: 001-75351 rev. *b page 20 of 30 ac test loads and waveforms figure 3. ac test loads and waveforms output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v l = 1.5v 3.3v all input pulses v ddq gnd 90% 10% 90% 10% ? 1 ns ? 1 ns (c) output r = 1667 ? r = 1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v l = 1.25v 2.5v all input pulses v ddq gnd 90% 10% 90% 10% ? 1 ns ? 1 ns (c) 3.3 v i/o test load 2.5 v i/o test load
cy7c1484bv33 document number: 001-75351 rev. *b page 21 of 30 switching characteristics over the operating range parameter [16, 17] description 250 mhz unit min max t power v dd (typical) to the first access [18] 1?ms clock t cyc clock cycle time 4 ? ns t ch clock high 2.0 ? ns t cl clock low 2.0 ? ns output times t co data output valid after clk rise ? 3.0 ns t doh data output hold after clk rise 1.3 ? ns t clz clock to low z [19, 20, 21] 1.3 ? ns t chz clock to high z [19, 20, 21] ?3.0ns t oev oe low to output valid ? 3.0 ns t oelz oe low to output low z [19, 20, 21] 0?ns t oehz oe high to output high z [19, 20, 21] ?3.0ns setup times t as address setup before clk rise 1.4 ? ns t ads adsc , adsp setup before clk rise 1.4 ? ns t advs adv setup before clk rise 1.4 ? ns t wes gw , bwe , bw x setup before clk rise 1.4 ? ns t ds data input setup before clk rise 1.4 ? ns t ces chip enable setup before clk rise 1.4 ? ns hold times t ah address hold after clk rise 0.4 ? ns t adh adsp , adsc hold after clk rise 0.4 ? ns t advh adv hold after clk rise 0.4 ? ns t weh gw , bwe , bw x hold after clk rise 0.4 ? ns t dh data input hold after clk rise 0.4 ? ns t ceh chip enable hold after clk rise 0.4 ? ns notes 16. timing reference level is 1.5 v when v ddq = 3.3 v and is 1.25 v when v ddq = 2.5 v. 17. test conditions shown in (a) of figure 3 on page 20 unless otherwise noted. 18. this part has an internal voltage regulator; t power is the time that the power is supplied above v dd(minimum) initially before a read or write operation can be initiated. 19. t chz , t clz ,t oelz , and t oehz are specified with ac test conditions shown in part (b) of figure 3 on page 20 . transition is measured 200 mv from steady-state voltage. 20. at any supplied voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user condi tions. device is designed to achieve high z before low z under the same system conditions. 21. this parameter is sampled and not 100% tested.
cy7c1484bv33 document number: 001-75351 rev. *b page 22 of 30 switching waveforms figure 4. read cycle timing [22] t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces g w, bwe,bw data out (dq) high-z t doh t co adv t oehz t co single read burst read t oev t oelz t chz burst wraps around to its initial state t advh t advs t weh t wes t adh t ads q(a2) q(a2 + 1) q(a2 + 2) q(a1) q(a2) q(a2 + 1) q(a3) q(a2 + 3) a2 a3 deselect cycle burst continued with new base address adv suspends burst dont care undefined x clz t note 22. on this diagram, when ce is low: ce 1 is low, ce 2 is high, and ce 3 is low. when ce is high: ce 1 is high, ce 2 is low, or ce 3 is high.
cy7c1484bv33 document number: 001-75351 rev. *b page 23 of 30 figure 5. write cycle timing [23, 24] switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces bwe, bw x adv burst read burst write d(a2) d(a2 + 1) d(a2 + 1) d(a3) d(a3 + 1) d(a3 + 2) d(a2 + 3) a2 a3 extended burst write d(a2 + 2) single write t adh t ads t adh t ads t oehz t advh t advs t weh t wes t dh t ds gw t weh t wes byte write signals are ignored for first cycle when adsp initiates burst adsc extends burst adv suspends burst dont care undefined d(a1) high-z data in (d) d ata out (q) notes 23. on this diagram, when ce is low: ce 1 is low, ce 2 is high, and ce 3 is low. when ce is high: ce 1 is high, ce 2 is low, or ce 3 is high. 24. full width write is initiated by either gw low; or by gw high, bwe low, and bw x low.
cy7c1484bv33 document number: 001-75351 rev. *b page 24 of 30 figure 6. read/write cycle timing [25, 26, 27] switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a2 t ceh t ces d ata out (q) high-z adv single write d(a3) a4 a5 a6 d(a5) d(a6) data in (d) burst read back-to-back reads high-z q(a2) q(a1) q(a4) q(a4+1) q(a4+2) t weh t wes q(a4+3) t oehz t dh t ds t oelz t clz t co back-to-back writes a1 bwe, bw x a3 dont care undefined notes 25. on this diagram, when ce is low: ce 1 is low, ce 2 is high, and ce 3 is low. when ce is high: ce 1 is high, ce 2 is low, or ce 3 is high. 26. the data bus (q) remains in high z following a write cycle unless a new read access is initiated by adsp or adsc . 27. gw is high.
cy7c1484bv33 document number: 001-75351 rev. *b page 25 of 30 figure 7. zz mode timing [28, 29] switching waveforms (continued) t zz i supply clk zz t zzrec a ll inputs (except zz) dont care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only notes 28. device must be deselected when entering zz mode. see truth table on page 8 for all possible signal conditions to deselect the device. 29. dqs are in high z when exiting zz sleep mode.
cy7c1484bv33 document number: 001-75351 rev. *b page 26 of 30 ordering information not all of the speed, package and temperat ure ranges are available. please contact your local sales representative or visit www.cypress.com for actual products offered. speed (mhz) ordering code package diagram part and package type operating range 250 CY7C1484BV33-250BZXC 51-85165 165-ball fbga (15 17 1.4 mm) pb-free commercial ordering code definitions temperature range: c = commercial = 0 c to +70 c x = pb-free package type: bz = 165-ball fbga speed grade: 250 mhz v33 = 3.3 v process technology: b ? errata fix pcn084636 part identifier: 1484 = dcd, 2 m 36 (72 mb) technology code: c = cmos marketing code: 7 = sram company id: cy = cypress c 1484 b - 250 c bz v33 x cy 7
cy7c1484bv33 document number: 001-75351 rev. *b page 27 of 30 package diagrams figure 8. 165-ball fbga (15 17 1.40 mm) (0.45 ball diameter) package outline, 51-85165 51-85165 *d
cy7c1484bv33 document number: 001-75351 rev. *b page 28 of 30 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal-oxide-semiconductor eia electronic industries alliance fbga fine-pitch ball grid array i/o input/output jedec joint electron devices engineering council jtag joint test action group lsb least significant bit msb most significant bit oe output enable sram static random access memory tap test access port tck test clock tdi test data-in tdo test data-out tms test mode select ttl transistor-transistor logic symbol unit of measure c degree celsius mhz megahertz a microampere ma milliampere mm millimeter ms millisecond mv millivolt ns nanosecond ? ohm % percent pf picofarad vvolt wwatt
cy7c1484bv33 document number: 001-75351 rev. *b page 29 of 30 document history page document title: cy7c1484bv33, 72-mbit (2 m 36) pipelined dcd sync sram document number: 001-75351 rev. ecn no. issue date orig. of change description of change ** 3478707 01/17/2012 gopa new data sheet. *a 3508646 01/25/2012 gopa changed status from preliminary to final. *b 3862706 01/09/2013 prit no technical updates. completing sunset review.
document number: 001-75351 rev. *b revised january 9, 2013 page 30 of 30 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1484bv33 ? cypress semiconductor corporation, 2012-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

▲Up To Search▲

Price & Availability of CY7C1484BV33-250BZXC

	To Download CY7C1484BV33-250BZXC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .